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Instruction set architectures
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11	Term-Level Verification of a Pipelined CISC Microprocessor Randal E. Bryant December, 2005 CMU-CS Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2006-01-09 17:18:43 Computer architecture Computing Computer hardware Central processing unit Classes of computers Instruction set architectures Microprocessors Instruction pipelining Reduced instruction set computing Program counter Instruction set Processor design
12	Ratio Games Raj Jain Washington University in Saint Louis Saint Louis, MOThese slides are available on-line at: Add to Reading List Source URL: www.cs.wustl.edu Language: English - Date: 2008-11-05 11:12:44 Computer architecture Religion Instruction set architectures Computing Classes of computers Reduced instruction set computing Raj Jain RISC-V Jain St. Louis
13	April 2, 2001 AGB Programming Manual Version 1.1  Nintendo of America Inc. Add to Reading List Source URL: cdn.preterhuman.net Language: English - Date: 2012-10-01 20:12:42 Computing Computer architecture Data transmission Universal asynchronous receiver/transmitter Cell Nintendo DS Microcontrollers Instruction set architectures
14	Building the IP Ecosystem by Thomas Harms The term System-on-a-Chip (SoC) defines both a product and a process. As a product, SoC defines specific, targeted applications and contains an entire system. An SoC product will Add to Reading List Source URL: www.steinwrites.com Language: English - Date: 2009-03-19 17:34:19 Computer architecture Electronic engineering Electronics System on a chip Instruction set architectures Electronic design Integrated circuits Computer buses Reuse CoreConnect ARC Application-specific integrated circuit
15	E cient Software-Based Fault Isolation Robert Wahbe Steven Lucco Thomas E. Anderson Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2003-04-04 15:00:43 Computing Computer architecture Computer engineering Central processing unit Instruction set architectures Assembly languages Processor register MIPS instruction set Instruction set Addressing mode Virtual memory CPU cache
16	Electronic Communications of the EASST VolumeProceedings of the Workshop on OCL and Textual Modelling (OCL 2011) Add to Reading List Source URL: gres.uoc.edu Language: English - Date: 2011-06-14 18:01:44 Computer architecture Computing Computer engineering Instruction set architectures Central processing unit Simulation software LISA Instruction set Assembly language ARM architecture Hardware description language Computer
17	eSi-1600 – 16-bit, low-cost & low-power CPU EnSilica’s eSi-1600 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance t Add to Reading List Source URL: www.avant-tek.com Language: English - Date: 2014-10-14 01:56:25 Computing Computer architecture Computer engineering Embedded microprocessors Instruction set architectures EnSilica ESi-RISC Central processing unit JTAG ARC 16-bit Reduced instruction set computing
18	Efficient Cryptography on RISC-V Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-11-30 11:00:03 Computer architecture Instruction set architectures Computing Reduced instruction set computing RISC-V Cryptography Cryptographic primitive Instruction set Institute for Applied Information Processing and Communications
19	The HP OpenVMS Approach to High Availability Computing Table of contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. What is High Availab Add to Reading List Source URL: www.stanq.com Language: English - Date: 2015-08-26 16:18:15 Computing Computer architecture Concurrent computing Hewlett-Packard Cluster computing Parallel computing OpenVMS Quality control Instruction set architectures VMScluster Computer cluster HP Integrity Servers
20	RI5CY: User Manual May 2016 Revision 0.9 Andreas Traber () Michael Gautschi () Add to Reading List Source URL: www.pulp-platform.org Language: English - Date: 2016-05-25 19:13:33 Computer architecture Instruction set architectures Computing Computer engineering Central processing unit Instruction set Reduced instruction set computing Program counter MIPI Debug Architecture ARM architecture

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